Can any one tell me which version of modelsim supports codecoverage option.
Actually i am using modelsim 6.3f[Special Edition] version. I face problems when trying do a codecoverage.

I would like to know the version number and edition number for both verilog and System verilog.

Regards,
Aathi

My question has to do with interfacing a Verilog testbench to a VHDL DUT. This is easy to do when the VHDL entity has normal port signals such as bit_vector, std_logic_vector, and std_logic. However to keep my design clean I make extensive use of records in VHDL. This has caused considerable headache when I try to instantiate the VHDL entity in the verilog testbench, which I still haven’t figured out how to do. I’m by no means a verilog expert but I did find out that verilog does not have an equivalent to records, just a way of faking them. I was wondering if the designers of Teal had run into the same problem and what solutions they ended up using?

Thanks,
Brian

Thanks,

Brian

Mike and I attended Mentor Graphics New England Users Group Meeting yesterday and mike did a small presentation about Teal and Truss. For reference these were the slides Mike presented. It’s always interesting to give a presentation and I think we’re getting better each time we try. This presentation I think better highlighted the thinking behind teal and truss while also giving a decent overview.

Regards,

/Robert

If you would like to track Truss and Teal more closely than the current release schedule, you can pull the code from the repository. Here’s how.

First, our svn repository is accessible ONLY by the svn+ssh method. Normal http style svn urls will not work at all. You will need to configure your svn client properly; the first step is to download our key If you are using PuTTY on Windows, download trusster-anon.ppk; if you’re using OpenSSH, download trusster-anon.key instead.

Next, put the key file in secure directory and chmod it 0400.

You’ll need to set the SVN_SSH environment variable for trusster as follows (for bash, other shells may be different):

# export SVN_SSH=”ssh -l trusster -i”

And test it:
# $SVN_SSH trusster.com

Should produce the following output:
( success ( 1 2 ( ANONYMOUS EXTERNAL ) ( edit-pipeline svndiff1 absent-entries commit-revprops merge-info ) ) )

Hit Ctrl+D to close the tunnel.

That’s pretty much it, all that is left to do is checkout the code:

# svn co svn+ssh://trusster.com/teal/trunk
# svn co svn+ssh://trusster.com/truss/trunk

If you’d rather use PuTTY, create a session for trusster.com called trusster-anon. Configure it to use the trusster-anon.ppk key as the session key, using “trusster” as the “auto login username”. Make sure you save the session. Use the session name in the svn url like so:

svn+ssh://trusster-anon/teal/trunk

My examples are coded in C# (an OOP that is like a fraternal twin to C++). C# Express 2005 is a free download from Microsoft and is easy to learn. I also have a C++ version, but have not used as much OOP.

I think the interesting notion here is that the simulator/hardware can run on a thread with verification on another — everything in OOP C++.

I am an old retired hardware guy self taught in C++ so I’m not up to speed with some of your lingo.
Hardware design and simulation are still in my blood.

First, the simulator does not use a programming language that has to be learned and compiled. Instead it is a collection of facilities ( flip-flops, registers, arrays, etc) that have Boolean/arithmetic statements describing their controls and inputs. The input phase assigns an ID# to each, the statements are parsed and a stack is created so the statements can be interpretatively evaluated at runtime.

At runtime objects are created and put in arrays or lists that are accessed by index or iterators.

Clocking is a C1/C2 scheme where C1 time determines the facility state that will be assigned at C2 time. Multiple clocks are allowed so that asynchronous, edge triggered, latch operations are permitted.

Functional delays (delay lines, long cables, etc) can be used.

Circuit delays are not used. Instead static timing analysis would be used to identify long paths that would determine cycle time. After all, placement in physical design will have major timing effects anyway.

The porting and wiring is implicit in the input statements so that back tracing the input can produce a net list or whatever is needed for synthesis. (Hypothesis)

The level of abstraction is a matter of the operators used in the statements. +, -, *, /, etc can be used at the system level, then later reduced to and/or/not operations..

There are C++ (Express and MFC) and C# versions implemenmted so that a driver could be added to generate inputs and verify outputs.

I do have running programs and several testcases available. ( Think I can upload them to a Web page for download or else post them as file attachments) The program is small and quick. It does need a simple GUI front end to isolate the user from syntax details.

I hope not to have wasted too much of your time, and welcome questions.

Thankyou, Karl Stevens

Apart from providing a preview of our style, they also provide documentation for our open-source libraries.

So to get a feel for what our books are like and to find out more details about our verification libraries teal and truss, and what “the dance” is all about, simply download either the C++ or SystemVerilog sections from our downloads page.

You can also access the chapters for teal and truss for C++ by following this link, or if you are interested in SystemVerilog follow this link.

So if these section are free, what else are in the books? Well, the section dealing with teal and truss is less then a 1/4 of the books. Most of the books could care less about our verification libraries but instead talk about how to best apply Object Oriented Programming (OOP) to Verification. We provide many code examples as well as lessons learned with the hope that you can avoid some of the pit-falls we encountered.

In fact, both our C++ and SystemVerilog verification books share the same format and are divided into four parts. The chapters provided for download are the second part of the book. In case you are curious, the four parts are:

• Part one provides and overview of Object Oriented Programming (OOP) concepts and conceptually looks at how a high level white-board block-diagram drawing can be turned into classes and code, as well as a short history of how verification has developed.
• Part two describes our open source verification libraries. We talk about our verification libraries in the books to show what a real, professional verification system looks like. Our hope is that people will find our libraries and ideas useful and adapt (parts of) them, or at least serve as inspiration or contrast too their actual environments. A lot of experience and industry best-practice ideas has gone into creating these libraries.
• Part three shows how to use OOP for Verification. It’s full of lessons learned, tips-and-tricks from years of experience using OOP in both HW verification and SW development fields and multitude of projects.
• Part four provides several complete verification environment examples too give the reader a sense for what an OOP verification environment looks like put together. As we provide the complete environment (including run scripts) we hope people can find useful code and ideas from them.

Happy reading!

Verification is increasingly complex, and SystemVerilog is one of the languages that the verification community is turning to. However, no language by itself can guarantee success without proper techniques. Object-oriented programming (OOP), with its focus on managing complexity, is ideally suited to this task.

With this handbook — the first to focus on applying OOP to SystemVerilog—we’ll show how to manage complexity by using layers of abstraction and base classes. By adapting these techniques, you will write more “reasonable” code, and build efficient and reusable verification components.

Both a learning tool and a reference, this handbook contains hundreds of real-world code snippets and three professional verification-system examples. You can copy and paste from these examples, which are all based on an open-source, vendor neutral
framework (with code freely available at www.trusster.com).

Learn about Object-oriented techniques such as these:

• Creating classes—code interfaces, factory functions, reuse
• Connecting classes—pointers, inheritance, channels
• Using “correct by construction”—strong typing, base classes
• Packaging it up—singletons, static methods, packages

“This handbook contains a lot of useful advice for any verification engineer wanting to create a class-based testbench, regardless of the framework/methodology used. I recommend Hardware Verification with SystemVerilog to anyone who wants a greater understanding of how best to use OOP with SystemVerilog.”

“This is a fantastic book that not only shows how to use SystemVerilog and Object-Oriented Programming for verification, but also provides practical examples that are open source!”

“I have been using SystemVerilog for two years in my research, and this is by far the best book I have found about how to achieve professional grade verification. I will apply these techniques on my future projects.”

I mentioned that top-down design is pretty much what we call ends-in design in our book. It’s just the way most people work. You iterate to a solution that works.

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This book, available through amazon and published by Springer is written by two engineers who do verification for a living. Hardware Verification with C++: A Practioner’s Handbook is a four-part tour of how to perform object-oriented hardware verification through simulation. This handbook goes beyond hype and theoretical discussions to show fully implemented examples, all provided as open-source code on the companion CD.

• Part I makes the case for C++, and shows what a standard verification system using object-oriented programming (OOP) looks like.
• Part II presents two open-source C++ libraries that enable efficient verification with C++:
  • Teal, a C++ to Verilog interface
  • Truss, a standard verification framework
• Part III is all about OOP, with examples from real verification projects.
• Part IV puts it all together, showing complete block-level and system-level verification systems.

Both a learning and a reference tool, the Handbook gives you everything you need to do hardware verification with C++ apart from a simulator—all provided as open-source on the companion CD.

“The handbook provides a clear understanding of object-oriented programming, and how it applies to hardware verification. It is clear to me that C++, together with Teal and Truss, could form a strong platform for the next generation of hardware verification.”

Dr. Stanley Hyduke, CEO of Aldec, Inc.

“With this book I feel confident I can constitute a verification team that could make good use of C++ for verification, with all the positive results I would need for success. That is a breakthrough!”

Bob Fredieu, VP of Research and development and Cofounder, Assertive Design

“Hardware verification complexity has grown to be a software effort, requiring advanced techniques such as OOP. With clear techniques and examples, this handbook guides the reader through the complexities of using OOP to create testbenches. Regardless of what language you use, this book will help sharpen your skills.”

Chris Spear, Verification Consultant, Synopsys, Inc.; Author of SystemVerilog for Verification

“A good book with great insight on the real-world problems faced by ASIC verification engineers every day. The authors use a humorous style to make this an easy read, while dealing effectively with complex issues.”

Dale Mosher, Director of ASIC Development