Hi,

This release supports the AXIOM simulator!!! This is a great news for both Trusster and Axiom. We'll have more official news about this soon.

Also, this release of Teal and Truss fixes a few bugs namely:
- The truss_vout object was not shutting down cleanly.
- The truss_shutdown object did not handle null test/testbench/watchdog pointers gracefully.
- VCS changed their string passing scheme, so the truss script was updated.
- VCS added support for interfaces in packages, so the examples were changed.

Let us know at support <> trusster <> com if there are any issues.

Hi,

We have just posted a new release of Teal and Truss (and the examples). There is not really any major changes in functionality, it's just this is the first release using the subversion system! Cool, eh? Feel free to browse the source code or download the new version.

Take Care,
mike

Hi,

I will be giving my Object Oriented Programming for Hardware Verification Demystified talk at DAC in the Aldec booth. Stop on by and say "Hi".

I'll also be showing off our latest book "Hardware Verification with SystemVerilog". It just got released today.

And if that wasn't enough, I'll be handing out temporary tattoos!

Take Care,
Mike

Today was a big day. We taped-out the book! Robert and I collated the quotes and the back cover text. At this point, the book's fate is in the hands of Springer. We already know of a few mistakes in the book, and I'm sure there will be a few more. But they are minor.

Richard has a good blog about the beginnings of top-down design (in the hardware domain). He talks here about an early experience with VHDL.

I mentioned that top-down design is pretty much what we call ends-in design in our book. It's just the way most people work. You iterate to a solution that works.

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So How did this Systemverilog Teal/truss come to be?

We first developed truss and teal in C++ as

• SystemVerilog wasn't stable enough when we started and
• C++ was better known to us then SystemVerilog.

Also, we wanted a clean environment first without any language or portability bias. Once we proved that our C++ environment was working for large projects it wasn't hard to port it to SystemVerilog.

A while ago I asked Max to take a look at our book. If you don't know, Max is one interesting person! In addition to writing such cool books as Bebop to the Boolean Boogie: An Unconventional Guide to Electronics and The Definitive Guide to How Computers Do Math : Featuring the Virtual DIY Calculator , he is working on a really great huge calculator.

Anyway, Max spent the weekend with the book and loved it! Here's his review: Programmable Logic DesignLine

Hi,

I noticed that many people are feeling the corporate push to "have a common platform". Check out a post on Cooley's DeepChip Company considers unifying Cadence/Synopsys/Mentor to one vendor Instead of unifying to one vendor, how about running under an environment that is cross platform and open source?