Trusster » Presentation http://www.trusster.com ...verify everything... Thu, 23 Dec 2010 15:09:06 +0000 en hourly 1 http://wordpress.org/?v=3.3.1 Webinar – Verification Code Longevity: Learn Expert Techniques http://www.trusster.com/verification/webinar-verification-code-longevity-learn-expert-techniques/ http://www.trusster.com/verification/webinar-verification-code-longevity-learn-expert-techniques/#comments Sat, 22 Aug 2009 20:11:03 +0000 Mike Mintz -------------------- North America ---------------------------------------- Date : August 27, 2009 Time : 11:00 am - 12:00 pm Pacific Daylight Time (USA) --------------------- Europe ---------------------------------------------- Date : August 27, 2009 Time : 3:00 pm - 4:00 pm Central European Summer Time ]]> I’ll be doing a webinar on how to make code last! It is based on the “Thinking OOP” chapter of our book.

——————– North America —————————————-
Date : August 27, 2009
Time : 11:00 am – 12:00 pm Pacific Daylight Time (USA)

——————— Europe ———————————————-
Date : August 27, 2009
Time : 3:00 pm – 4:00 pm Central European Summer Time


Abstract :
It seems that we always have to rewrite verification code that we did on
a previous project. Why? What can we do to minimize code changes? In
this webinar, international author Mike Mintz shares Expert Techniques,
based on OOP (Object Oriented Programming) that he uses to make code
last. We’ll take a look at how to write adaptable monitors and checkers.
Mike will show how to maximize the probability that your code can be
adapted to other projects.

Agenda :

* Introduction
* What is bit rot?
* Adaptable versus Reusable code
* Minimizing your assumptions to Maximize Adaptability
* Canonical Monitors and Checkers
* Aldec RTL Simulators & Design Rule Checking
* Question and Answer Session

View All Aldec Events: http://www.aldec.com/Events

]]> http://www.trusster.com/verification/webinar-verification-code-longevity-learn-expert-techniques/feed/ 0 Reviewers for our upcoming SystemVerilog book wanted! http://www.trusster.com/presentation/reviewers-for-our-upcoming-systemverilog-book-wanted!/ http://www.trusster.com/presentation/reviewers-for-our-upcoming-systemverilog-book-wanted!/#comments Wed, 30 Nov -0001 00:00:00 +0000 read we're working on re-writing our book for SystemVerilog. We feel there aren't that many good independent books or solutions out there, especially ones that focus on Object Oriented Programming and honestly talk about the current state of the SV language. In addition, the book provides documentation for our SV verification libraries Teal and Truss. We (well mostly Mike) have made good progress and we are now getting closer to being done. At this stage we could use your input. As always the dead-line is tight so we need this done over the next two weeks to meet our obligations. We can't promise you any rewards more then a mention in the book and our gratitude. If you are interested we will send you a draft and ask that you to focus on one or two chapters. ]]> As you might have read we’re working on re-writing our book for SystemVerilog. We feel there aren’t that many good independent books or solutions out there, especially ones that focus on Object Oriented Programming and honestly talk about the current state of the SV language. In addition, the book provides documentation for our SV verification libraries Teal and Truss.

We (well mostly Mike) have made good progress and we are now getting closer to being done. At this stage we could use your input. As always the dead-line is tight so we need this done over the next two weeks to meet our obligations. We can’t promise you any rewards more then a mention in the book and our gratitude.

If you are interested we will send you a draft and ask that you to focus on one or two chapters. You can pick any chapters from the list below. We will send you the draft as a PDF, and you can submit your comments through e-mail or post them in this forum. We are interested both in technical clarity as well as grammar and spelling, and please look through the source code in the examples for any errors or omissions.

The table of contents is:

  • Chapter 1: Introduction
  • Chapter 2: Why SystemVerilog?
  • Chapter 3: OOP, SystemVerilog and Verification
  • Chapter 4: A Layered Approach
  • Chapter 5: Teal Basics
  • Chapter 6: Truss: A Standard Verification Framwork
  • Chapter 7: Truss Flow
  • Chapter 8: Truss Example
  • Chapter 9: Thinking OOP
  • Chapter 10: Designing with OOP
  • Chapter 11: OOP Classes
  • Chapter 12: OOP Connections
  • Chapter 13: Coding OOP
  • Chapter 14: Block Level Testing
  • Chapter 15: Chip Level Testing
  • Chapter 16: Things to Remember

If you are interested please post the one or two chapters that you would like to review in this forum (or send us an e-mail) and we will send you an e-mail with the pdf’s .

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