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Archive for category Teal

Webinar – Verification Code Longevity: Learn Expert Techniques

Aug 22

Posted by Mike Mintz in Presentation, Teal, Truss, Verification | Comments off

I’ll be doing a webinar on how to make code last! It is based on the “Thinking OOP” chapter of our book.

——————– North America —————————————-
Date : August 27, 2009
Time : 11:00 am – 12:00 pm Pacific Daylight Time (USA)

——————— Europe ———————————————-
Date : August 27, 2009
Time : 3:00 pm – 4:00 pm Central European Summer Time


Abstract :
It seems that we always have to rewrite verification code that we did on
a previous project. Why? What can we do to minimize code changes? In
this webinar, international author Mike Mintz shares Expert Techniques,
based on OOP (Object Oriented Programming) that he uses to make code
last. We’ll take a look at how to write adaptable monitors and checkers.
Mike will show how to maximize the probability that your code can be
adapted to other projects.

Agenda :

* Introduction
* What is bit rot?
* Adaptable versus Reusable code
* Minimizing your assumptions to Maximize Adaptability
* Canonical Monitors and Checkers
* Aldec RTL Simulators & Design Rule Checking
* Question and Answer Session

View All Aldec Events: http://www.aldec.com/Events

Run erro by truss/teal in systemverilog using ncsim

Dec 1

Posted by in Teal | Comments off

HI,
I’m currently using Cadence Incisive (ncsim) to run the example block_uart in the “truss systemverilog version 1.62 ” ,which gets some compile errors. It seems the script truss about ncsim in the directory of bin has some erros.
the part of the script:
elsif (uc $ENV{SIM} eq “NCSIM”){
#
# NCSIM
#
………
$compile_hdl = (“cd $RESULT_DIR; mkdir ncvlog_lib; ” .
“echo DEFINE ncvlog_lib ./ncvlog_lib > cds.lib; ” .
“echo DEFINE WORK ncvlog_lib > hdl.var; ” .
“ncvlog $ENV{\”PROJECT_HOME\”}/verification/testbench/$config/testbench.v -WORK ncvlog_lib ” .
“-f $ENV{\”PROJECT_HOME\”}/verification/testbench/$config/hdl_paths.ncsim ;” .
“ncelab -REDUCE_MESSAGES -NOCOPYRIGHT -ARR_ACCESS -ACCWARN -LIBNAME ncvlog_lib -LOGFILE ncelab.log -access +RWC ncvlog_lib.top -SNAPSHOT ncvlog_lib.ncvlog_lib:ncvlog_lib”);
truss_system ($compile_hdl);
}

I had changed it by add some args ,eg: -sv, but many errors again. Do you guys has a better success script
to support ncsim in systemverilog?

Thanks,
wheater

HOWTO: Configure SVN for read-only access

Jan 30

Posted by admin in Teal, Truss | Comments off

The source code to Teal and Truss is currently available through subversion, a popular source code control system. Currently, only Mike and Robert have commit privileges, though they are happy to accept patches from the community.

If you would like to track Truss and Teal more closely than the current release schedule, you can pull the code from the repository. Here’s how.

First, our svn repository is accessible ONLY by the svn+ssh method. Normal http style svn urls will not work at all. You will need to configure your svn client properly; the first step is to download our key If you are using PuTTY on Windows, download trusster-anon.ppk; if you’re using OpenSSH, download trusster-anon.key instead.

Next, put the key file in secure directory and chmod it 0400.

You’ll need to set the SVN_SSH environment variable for trusster as follows (for bash, other shells may be different):

# export SVN_SSH=”ssh -l trusster -i”

And test it:
# $SVN_SSH trusster.com

Should produce the following output:
( success ( 1 2 ( ANONYMOUS EXTERNAL ) ( edit-pipeline svndiff1 absent-entries commit-revprops merge-info ) ) )

Hit Ctrl+D to close the tunnel.

That’s pretty much it, all that is left to do is checkout the code:

# svn co svn+ssh://trusster.com/teal/trunk
# svn co svn+ssh://trusster.com/truss/trunk

If you’d rather use PuTTY, create a session for trusster.com called trusster-anon. Configure it to use the trusster-anon.ppk key as the session key, using “trusster” as the “auto login username”. Make sure you save the session. Use the session name in the svn url like so:

svn+ssh://trusster-anon/teal/trunk

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Modelsim only support 2 call stack for automatic task?

Nov 30

Posted by in Teal | 3 Comments

Hi everybody,

I am now studying system verilog. Many thanks to Mike and Rober for their open and sharing!

I am using modelsim 6.2C to perform the simulation. But it seems that
Modelsim only support 2 call stack for automatic task. If it calls its self third time, the stack address of the third call will be the same to the second call. So when the third call returns, modelsim runs deadly.

:-(

Usage of channels in examples

Jul 20

Posted by in Teal | 1 Comment

Hi,

Currently looking into the block_uart example (SystemVerilog) to check whether we should start using the truss library (Don’t have the book yet :-( . I am to SystemVerilog so maybe a stupid question, but why is in the example a uart_channel class defined which is almost equal to truss_channel iso instantiating an uart_channel of type truss_channel?

Kind Regards,
Roger.

Updated examples?

Jun 28

Posted by in Teal | 1 Comment

In looking through some of the examples, it looks like there are several files missing from the sv_2_19_2007.tar_.gz download. The alu example looks incomplete (missing generator, etc in the vip directory), and the uart examples seem to be missing some files (uart_basic_test_component, etc).

Will there be an updated download available soon?

Thanks.

Truss SystemVerilog support for Cadence?

Jun 27

Posted by in Teal | 1 Comment

I’m currently using Cadence Incisive (ncsim), and am trying to get the SystemVerilog Truss/Teal to compile. I have version 6.11-s001, and I get all kinds of SystemVerilog errors.

Do you guys support, or plan to support Cadence? If so, is there a script that I should try?

Thanks,
Josh

Reviewers for our upcoming SystemVerilog book wanted!

Feb 24

Posted by in Teal | 1 Comment

!!! Call for reviewers has come to and end (see comment below) !!!

As you might have read we’re working on re-writing our book for SystemVerilog. We feel there aren’t that many good independent books or solutions out there, especially ones that focus on Object Oriented Programming and honestly talk about the current state of the SV language. In addition, the book provides documentation for our SV verification libraries Teal and Truss.

We (well mostly Mike) have made good progress and we are now getting closer to being done. At this stage we could use your input. As always the dead-line is tight so we need this done over the next two weeks to meet our obligations. We can’t promise you any rewards more then a mention in the book and our gratitude.

If you are interested we will send you a draft and ask that you to focus on one or two chapters. You can pick any chapters from the list below. We will send you the draft as a PDF, and you can submit your comments through e-mail or post them in this forum. We are interested both in technical clarity as well as grammar and spelling, and please look through the source code in the examples for any errors or omissions.

The table of contents is:

  • Chapter 1: Introduction
  • Chapter 2: Why SystemVerilog?
  • Chapter 3: OOP, SystemVerilog and Verification
  • Chapter 4: A Layered Approach
  • Chapter 5: Teal Basics
  • Chapter 6: Truss: A Standard Verification Framwork
  • Chapter 7: Truss Flow
  • Chapter 8: Truss Example
  • Chapter 9: Thinking OOP
  • Chapter 10: Designing with OOP
  • Chapter 11: OOP Classes
  • Chapter 12: OOP Connections
  • Chapter 13: Coding OOP
  • Chapter 14: Block Level Testing
  • Chapter 15: Chip Level Testing
  • Chapter 16: Things to Remember

If you are interested please post the one or two chapters that you would like to review in this forum (or send us an e-mail) and we will send you an e-mail with the pdf’s .