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Archive for category Truss

Webinar – Verification Code Longevity: Learn Expert Techniques

Aug 22

Posted by Mike Mintz in Presentation, Teal, Truss, Verification | Comments off

I’ll be doing a webinar on how to make code last! It is based on the “Thinking OOP” chapter of our book.

——————– North America —————————————-
Date : August 27, 2009
Time : 11:00 am – 12:00 pm Pacific Daylight Time (USA)

——————— Europe ———————————————-
Date : August 27, 2009
Time : 3:00 pm – 4:00 pm Central European Summer Time


Abstract :
It seems that we always have to rewrite verification code that we did on
a previous project. Why? What can we do to minimize code changes? In
this webinar, international author Mike Mintz shares Expert Techniques,
based on OOP (Object Oriented Programming) that he uses to make code
last. We’ll take a look at how to write adaptable monitors and checkers.
Mike will show how to maximize the probability that your code can be
adapted to other projects.

Agenda :

* Introduction
* What is bit rot?
* Adaptable versus Reusable code
* Minimizing your assumptions to Maximize Adaptability
* Canonical Monitors and Checkers
* Aldec RTL Simulators & Design Rule Checking
* Question and Answer Session

View All Aldec Events: http://www.aldec.com/Events

Accellera Verification Intellectual Property Technical Subcommittee

Jun 9

Posted by in Truss | 4 Comments

What about the Truss/Teal donation to the committee ?

Road map for components classes

Apr 1

Posted by in Truss | 3 Comments

Hi Mike,

I am a new comer to the open source field for verification.

I have previously used Vera and its RVM methodology. I was really happy with the way the project terned out.

I was comparing the RVM and truss features briefly.

It seems very similar. However, I had a question questions on missing features and the timeline of its roadmap if under development.

1. Virtual ports in Vera. They were very useful for reusability. Do we have something similar ?
2. Random Constraint solver
3. Functional coverage

Can you please comment on the same. Sorry if its on the website and I missed them.

Maybe we can make a small document noting difference b/w RVM (similar such methodologies) and truss. This will give a new adopter more confidence in the infrastructure that you provide.

Thanks again for your efforts.

-Shamik

Where is teal/truss heading to (VHDL, SystemVerilog)?

Feb 19

Posted by in Truss | 6 Comments

Hi,

I was wondering where teal/truss is heading to?

In the blog at this page I read that there is a new book in queue about SystemVerilog. What does that mean in terms of using the framework? I assume it requires a simulator that supports SystemVerilog, not like the C++ approach that works for the verification part by itself and interacts over PLI with a Verilog simulator?

As SystemVerilog is getting more support by simulator vendors, will that put more emphasis on the SystemVerilog part of teal/truss as well? I mean, will we see the support of the C++ part reduce?

In the forum of the verification guild I read in a post of last year that there is some VHDL support planned. What is the status on that? Is that still a goal?

Thanks for the information.

Cheers,

Guenter