Run across a problem recently where I from teal had to drive a bi-directional verilog wire that should model “wire-and” functionality.
Basically the wire was pulled high in the verilog testbench (tri1). So to set the wire you should either drive it ’0′ or release it to get a ’1′.
The Teal vreg class don’t model this by default but it was easy to create a small class that modifies the vreg class to add this functionality
The code looks like this, note it only works for bits and not busses.
class wand : public vreg{
public:
wand(const std::string& n): vreg(n)
{ assert ( (bit_length() == 1)); };
virtual ~wand(){};
wand& operator= (const reg& rhs)
{
vreg::operator= (rhs);
if (rhs.to_int() == 1) {
vreg::release();
}
return *this;
};
};
Note! this assumes pull up of the actual signal in the testbench
Having bit wise wire and is useful in protocols like i2c and CAN.
/Robert
