Verilog Testbench with VHDL DUT
Posted July 3rd, 2008 by btm
I wasn't quite sure where to post this in the forum so here it goes.
My question has to do with interfacing a Verilog testbench to a VHDL DUT. This is easy to do when the VHDL entity has normal port signals such as bit_vector, std_logic_vector, and std_logic. However to keep my design clean I make extensive use of records in VHDL. This has caused considerable headache when I try to instantiate the VHDL entity in the verilog testbench, which I still haven't figured out how to do. I'm by no means a verilog expert but I did find out that verilog does not have an equivalent to records, just a way of faking them. I was wondering if the designers of Teal had run into the same problem and what solutions they ended up using?
Thanks,
Brian
Comments
Mixed language simulation
Mixed language simulation support at the VHDL /Verilog (IEEE 1364) boundary is at the discretion of the simulator that you are using.
Check first with your simulator vendor for what is supported and what isn't when mixing VHDL and Verilog.
You are correct in stating that Verilog does not have a direct equivalent for VHDL records which makes it tough connecting the two together.
However there are tools in the market that support mixed SystemVerilog and VHDL simulations. In systemVerilog, the closest equivalent to a VHDL record is a struct.
Some tools allow direct connection between records and structs but you need to check first with your simulation tool vendor to know the exact limitations (if any).
Gabriel