Trusster

…verify everything…

Mentor Graphics New England User Group Meeting Presentation

May 1

Posted by admin in Verification | Comments off

Mike and I attended Mentor Graphics New England Users Group Meeting yesterday and mike did a small presentation about Teal and Truss. For reference these were the slides Mike presented. It’s always interesting to give a presentation and I think we’re getting better each time we try. This presentation I think better highlighted the thinking behind teal and truss while also giving a decent overview.

Regards,

/Robert

Road map for components classes

Apr 1

Posted by in Truss | 3 Comments

Hi Mike,

I am a new comer to the open source field for verification.

I have previously used Vera and its RVM methodology. I was really happy with the way the project terned out.

I was comparing the RVM and truss features briefly.

It seems very similar. However, I had a question questions on missing features and the timeline of its roadmap if under development.

1. Virtual ports in Vera. They were very useful for reusability. Do we have something similar ?
2. Random Constraint solver
3. Functional coverage

Can you please comment on the same. Sorry if its on the website and I missed them.

Maybe we can make a small document noting difference b/w RVM (similar such methodologies) and truss. This will give a new adopter more confidence in the infrastructure that you provide.

Thanks again for your efforts.

-Shamik

HOWTO: Configure SVN for read-only access

Jan 30

Posted by admin in Teal, Truss | Comments off

The source code to Teal and Truss is currently available through subversion, a popular source code control system. Currently, only Mike and Robert have commit privileges, though they are happy to accept patches from the community.

If you would like to track Truss and Teal more closely than the current release schedule, you can pull the code from the repository. Here’s how.

First, our svn repository is accessible ONLY by the svn+ssh method. Normal http style svn urls will not work at all. You will need to configure your svn client properly; the first step is to download our key If you are using PuTTY on Windows, download trusster-anon.ppk; if you’re using OpenSSH, download trusster-anon.key instead.

Next, put the key file in secure directory and chmod it 0400.

You’ll need to set the SVN_SSH environment variable for trusster as follows (for bash, other shells may be different):

# export SVN_SSH=”ssh -l trusster -i”

And test it:
# $SVN_SSH trusster.com

Should produce the following output:
( success ( 1 2 ( ANONYMOUS EXTERNAL ) ( edit-pipeline svndiff1 absent-entries commit-revprops merge-info ) ) )

Hit Ctrl+D to close the tunnel.

That’s pretty much it, all that is left to do is checkout the code:

# svn co svn+ssh://trusster.com/teal/trunk
# svn co svn+ssh://trusster.com/truss/trunk

If you’d rather use PuTTY, create a session for trusster.com called trusster-anon. Configure it to use the trusster-anon.ppk key as the session key, using “trusster” as the “auto login username”. Make sure you save the session. Use the session name in the svn url like so:

svn+ssh://trusster-anon/teal/trunk

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New Release of SystemVerilog Teal and Truss

Dec 26

Posted by in Uncategorized | Comments off

Hi,

This release supports the AXIOM simulator!!! This is a great news for both Trusster and Axiom. We’ll have more official news about this soon.

Also, this release of Teal and Truss fixes a few bugs namely:
- The truss_vout object was not shutting down cleanly.
- The truss_shutdown object did not handle null test/testbench/watchdog pointers gracefully.
- VCS changed their string passing scheme, so the truss script was updated.
- VCS added support for interfaces in packages, so the examples were changed.

Let us know at support <> trusster <> com if there are any issues.

Take Care,
Mike

Verification Framework article published over at SCD-source

Dec 14

Posted by in Uncategorized | Comments off

While writing our two books, Mike and I frequently discussed not only the motivations for creating individual verification components but also how the should “look” for the end-user. Our discussion was always centered around usability for us verification engineers, so presenting a simple, clean code-interface was more important then simplifying the internals of Teal and Truss. (I’m not convinced all verification environment I’ve seen think that way…)

Mike and I was recently talking to Peggy Aycinena about Teal and Truss and it motivated Mike enough to put pen to paper (or is it key strokes to screen?) and write a couple of articles talking about why our code looks the way it does, one has now been published and the way, Mike also contributed a completely different recipe for success to Peggy!

As a result of this discussion, the first of two articles have recently been published over at SCD-source where Richard Goering works nowadays.

So to read more about why our code looks the way it does click over to SCD-Source. We would love to hear your comments afterwards!

Regards,

Robert

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[Trusster Announcements] Experiences with Teal and Truss

Dec 10

Posted by in Uncategorized | Comments off

Category: Trusster Announcements

Roles: authenticated user

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mike sent out a mass e-mail from http://www.trusster.com/.

Hi,

Here is a post on comp.lang.verilog where a person asks for users of
Teal/Truss, in C++ or SystemVerilog to speak up.

If you are, or know of, companies using teal/truss, please post a reply !

Heck even if you have comments good or bad about teal/truss, go ahead and
make them public.

Thanks,
Mike

http://groups.google.com/group/comp.lang.verilog/browse_thread/thread/d8013535c5725eca?hl=en

Experiences with Teal and Truss

Dec 7

Posted by in Uncategorized | Comments off

Hi,

Here is a post on comp.lang.verilog where a person asks for users of Teal/Truss, in C++ or SystemVerilog to speak up.

If you are, or know of, companies using teal/truss, please post a reply !

Heck even if you have comments good or bad about teal/truss, go ahead and make them public.

Thanks,
Mike

http://groups.google.com/group/comp.lang.verilog/browse_thread/thread/d8013535c5725eca?hl=en

Modelsim only support 2 call stack for automatic task?

Nov 30

Posted by in Teal | 3 Comments

Hi everybody,

I am now studying system verilog. Many thanks to Mike and Rober for their open and sharing!

I am using modelsim 6.2C to perform the simulation. But it seems that
Modelsim only support 2 call stack for automatic task. If it calls its self third time, the stack address of the third call will be the same to the second call. So when the third call returns, modelsim runs deadly.

:-(

Use of OOP to eliminate need to compile C++ simulation

Oct 6

Posted by admin in Verification | 4 Comments

I would appreciate your comments on a different approach to hardware simulation.

My examples are coded in C# (an OOP that is like a fraternal twin to C++). C# Express 2005 is a free download from Microsoft and is easy to learn. I also have a C++ version, but have not used as much OOP.

I think the interesting notion here is that the simulator/hardware can run on a thread with verification on another — everything in OOP C++.

I am an old retired hardware guy self taught in C++ so I’m not up to speed with some of your lingo.
Hardware design and simulation are still in my blood.

First, the simulator does not use a programming language that has to be learned and compiled. Instead it is a collection of facilities ( flip-flops, registers, arrays, etc) that have Boolean/arithmetic statements describing their controls and inputs. The input phase assigns an ID# to each, the statements are parsed and a stack is created so the statements can be interpretatively evaluated at runtime.

At runtime objects are created and put in arrays or lists that are accessed by index or iterators.

Clocking is a C1/C2 scheme where C1 time determines the facility state that will be assigned at C2 time. Multiple clocks are allowed so that asynchronous, edge triggered, latch operations are permitted.

Functional delays (delay lines, long cables, etc) can be used.

Circuit delays are not used. Instead static timing analysis would be used to identify long paths that would determine cycle time. After all, placement in physical design will have major timing effects anyway.

The porting and wiring is implicit in the input statements so that back tracing the input can produce a net list or whatever is needed for synthesis. (Hypothesis)

The level of abstraction is a matter of the operators used in the statements. +, -, *, /, etc can be used at the system level, then later reduced to and/or/not operations..

There are C++ (Express and MFC) and C# versions implemenmted so that a driver could be added to generate inputs and verify outputs.

I do have running programs and several testcases available. ( Think I can upload them to a Web page for download or else post them as file attachments) The program is small and quick. It does need a simple GUI front end to isolate the user from syntax details.

I hope not to have wasted too much of your time, and welcome questions.

Thankyou, Karl Stevens

Book excerpt on Teal and Truss available!

Oct 2

Posted by admin in Verification | Comments off

Hardware Verification with C++ Book Cover Hardware Verification with SystemVerilog Book CoverWe’re happy announce that the teal and truss section of both our C++ and SystemVerilog books are on the downloads page!

Apart from providing a preview of our style, they also provide documentation for our open-source libraries.

So to get a feel for what our books are like and to find out more details about our verification libraries teal and truss, and what “the dance” is all about, simply download either the C++ or SystemVerilog sections from our downloads page.

You can also access the chapters for teal and truss for C++ by following this link, or if you are interested in SystemVerilog follow this link.

So if these section are free, what else are in the books? Well, the section dealing with teal and truss is less then a 1/4 of the books. Most of the books could care less about our verification libraries but instead talk about how to best apply Object Oriented Programming (OOP) to Verification. We provide many code examples as well as lessons learned with the hope that you can avoid some of the pit-falls we encountered.

In fact, both our C++ and SystemVerilog verification books share the same format and are divided into four parts. The chapters provided for download are the second part of the book. In case you are curious, the four parts are:

  • Part one provides and overview of Object Oriented Programming (OOP) concepts and conceptually looks at how a high level white-board block-diagram drawing can be turned into classes and code, as well as a short history of how verification has developed.
  • Part two describes our open source verification libraries. We talk about our verification libraries in the books to show what a real, professional verification system looks like. Our hope is that people will find our libraries and ideas useful and adapt (parts of) them, or at least serve as inspiration or contrast too their actual environments. A lot of experience and industry best-practice ideas has gone into creating these libraries.
  • Part three shows how to use OOP for Verification. It’s full of lessons learned, tips-and-tricks from years of experience using OOP in both HW verification and SW development fields and multitude of projects.
  • Part four provides several complete verification environment examples too give the reader a sense for what an OOP verification environment looks like put together. As we provide the complete environment (including run scripts) we hope people can find useful code and ideas from them.

Happy reading!