I would appreciate your comments on a different approach to hardware simulation.
My examples are coded in C# (an OOP that is like a fraternal twin to C++). C# Express 2005 is a free download from Microsoft and is easy to learn. I also have a C++ version, but have not used as much OOP.
I think the interesting notion here is that the simulator/hardware can run on a thread with verification on another — everything in OOP C++.
I am an old retired hardware guy self taught in C++ so I’m not up to speed with some of your lingo.
Hardware design and simulation are still in my blood.
First, the simulator does not use a programming language that has to be learned and compiled. Instead it is a collection of facilities ( flip-flops, registers, arrays, etc) that have Boolean/arithmetic statements describing their controls and inputs. The input phase assigns an ID# to each, the statements are parsed and a stack is created so the statements can be interpretatively evaluated at runtime.
At runtime objects are created and put in arrays or lists that are accessed by index or iterators.
Clocking is a C1/C2 scheme where C1 time determines the facility state that will be assigned at C2 time. Multiple clocks are allowed so that asynchronous, edge triggered, latch operations are permitted.
Functional delays (delay lines, long cables, etc) can be used.
Circuit delays are not used. Instead static timing analysis would be used to identify long paths that would determine cycle time. After all, placement in physical design will have major timing effects anyway.
The porting and wiring is implicit in the input statements so that back tracing the input can produce a net list or whatever is needed for synthesis. (Hypothesis)
The level of abstraction is a matter of the operators used in the statements. +, -, *, /, etc can be used at the system level, then later reduced to and/or/not operations..
There are C++ (Express and MFC) and C# versions implemenmted so that a driver could be added to generate inputs and verify outputs.
I do have running programs and several testcases available. ( Think I can upload them to a Web page for download or else post them as file attachments) The program is small and quick. It does need a simple GUI front end to isolate the user from syntax details.
I hope not to have wasted too much of your time, and welcome questions.
Thankyou, Karl Stevens
#1 by mike on October 8th, 2007
Hi Karl,
This is an interesting idea. It would be neat to find a verilog or vhdl parser and marry it to your technology. Have you seen the verilator code base (http://www.veripool.com/verilator.html)?
Interested in the code examples Feel free to post your examples as an attachment or send them to support <> trusster.com .
If you are considering releasing the simulator as open source, Robert and I would consider setting up a web page for you under trusster.
Take care,
Mike
#2 by karl on October 11th, 2007
I will be glad to send the code , the question is the amount — the most complete would be a Visual C++ Express solution(s), but there are a couple of .pch files (about 4MB each). I will delete them, the solution would have to be built in order to run, but at least you can see the source for my two classes and the test cases. I will work on this.
I have uploaded 3 zip folders to http://mysite.verizon.net/vzeosqt4/simplesimin
Testcases are what I used for debug.
FLD takes each hex digit from one 16 bit reg and puts it in each digit of another.
UP is a crude microprocessor that uses Rom for control and has a classical Ram.
The rest are misc types using multiple clocks, delays and variable statements.
Goform.exe does the simulation. Open a testcase and select the input file to run.
InputForm is similar, select the testcase input fuile and it will parse and index the statements.
#3 by karl on October 9th, 2007
I could not attach a .cpp file, so renamed to .txt, only sent the sim class source. I will work on a web page so you can download and execute everything. Will post a link when (if) I succeed.
Thanks for your interest, Karl
#4 by karl on October 13th, 2007
I found an fscanf bug in the original go form.
The download file has been fixed.
I am including a new testcase here. I coded a VHDL example for a FSM. Hope its interesting.
// — cocurrent process#1: state registers
// state_reg: process(clock, reset)
// begin
//if (reset=’1′) then
// current_state < = S0;
//elsif (clock'event and clock='1') then
// current_state <= next_state;
//end if;
// end process;
// -- cocurrent process#2: combinational logic
// comb_logic: process(current_state, a)
// begin
//-- use case statement to show the
//-- state transistion
//case current_state is
// when S0 => x < = '0';
// if a='0' then
// next_state <= S0;
// elsif a ='1' then
// next_state <= S1;
// end if;
// when S1 => x < = '0';
// if a='0' then
// next_state <= S1;
// elsif a='1' then
// next_state <= S2;
// end if;
// when S2 => x < = '0';
// if a='0' then
// next_state <= S2;
// elsif a='1' then
// next_state <= S3;
// end if;
// when S3 => x < = '1';
// if a='0' then
// next_state <= S3;
// elsif a='1' then
// next_state <= S0;
// end if;
// when others =>
// x < = '0';
// next_state <= S0;
//end case;
// -- cocurrent process#1: state registers
// state_reg: process(clock, reset)
// begin
//if (reset='1') then
// current_state <= S0;
//elsif (clock'event and clock='1') then
// current_state <= next_state;
//end if;
// end process;
// -- cocurrent process#2: combinational logic
// comb_logic: process(current_state, a)
// begin
//-- use case statement to show the
//-- state transistion
//case current_state is
// when S0 => x < = '0';
// if a='0' then
// next_state <= S0;
// elsif a ='1' then
// next_state <= S1;
// end if;
// when S1 => x < = '0';
// if a='0' then
// next_state <= S1;
// elsif a='1' then
// next_state <= S2;
// end if;
// when S2 => x < = '0';
// if a='0' then
// next_state <= S2;
// elsif a='1' then
// next_state <= S3;
// end if;
// when S3 => x < = '1';
// if a='0' then
// next_state <= S3;
// elsif a='1' then
// next_state <= S0;
// end if;
// when others =>
// x <= ‘0′;
// next_state <= S0;
//end case;
clk.0 @ 0.2
clk.1 @ 1.2
S0.0 @0
S1.1 @ 0 //Set each state to a unique value because current_state will be set to the appropriate value
S2.2 @ 0
S3.3 @0
a.1 @ 4.6
a.0 @ 5.6
reset.1 @ 4
reset.0 @ 5
\c1?!clk
\c2?clk
current_state:S0 ? (current_state == S3)&a | reset
current_state:S1 ? (current_state == S0)&a
current_state:S2 ? (current_state == S1)&a
current_state:S3 ? (current_state == S2)&a