I recently got an e-mail from a friend that said he saw our book(s) on books24×7. The book is here.
You can read both our books on their site. Now your company has to have a subscription, but there are thousands of books there. I’ve been noodling around on their site and its really neat.
Sep 2
We have finally updated the Content Management System running our website. The old site became unmanageable for two over-worked engineers. With this new system we will have better control over spam together with better more integrated discussion forums. We also like the layout better. Please help us improve our site by reporting any issues you find.
To our registered users: While we where able to propagate all current users we couldn’t propagate the passwords so please keep an eye out for an e-mail with information on your new temporary password.
It is out intent to bring our site back to life and hopefully over time bring our forums back alive. Both Mike and I are still heavily if quietly involved with Teal and Truss. We use it in our daily professional lives. Mike currently use our C++ (and SystemC) libraries and I use our System Verilog version. Both incarnations are rather stable at this point and provide a great starting point for powerful but simple to use DV environment.
Regards
Robert
I’ll be doing a webinar on how to make code last! It is based on the “Thinking OOP” chapter of our book.
Abstract :
It seems that we always have to rewrite verification code that we did on
a previous project. Why? What can we do to minimize code changes? In
this webinar, international author Mike Mintz shares Expert Techniques,
based on OOP (Object Oriented Programming) that he uses to make code
last. We’ll take a look at how to write adaptable monitors and checkers.
Mike will show how to maximize the probability that your code can be
adapted to other projects.
Agenda :
* Introduction
* What is bit rot?
* Adaptable versus Reusable code
* Minimizing your assumptions to Maximize Adaptability
* Canonical Monitors and Checkers
* Aldec RTL Simulators & Design Rule Checking
* Question and Answer Session
View All Aldec Events: http://www.aldec.com/Events
Jul 9
I recently got an e-mail asking about copying objects and decided it would be a great blog post.
Specifically, the question asked about the differences between deep versus shallow copy and when one should choose one technique versus another.
The short answer is there is no right answer. The long answer, well, is a little longer…
In any Object-based system, copying an object is not a trivial exercise. As we talked about in the OOP Connections chapter, your verification system is a mesh of objects. Copying a piece of that mesh is tricky. But even beyond that is the seemingly simple task of copying data.
Suppose you are trying to verify a SOC that moves data to and from some interfaces (RAM, ethernet, PCI, etc). You probably have the classic “generator connected to driver and checker through a channel” model.
Before you have to consider shallow versus deep copy, you have to decide if you want to copy the data. In general, you do want to copy the data, but there is at least one case where you do not. This is the case where the driver and the checker need to communicate some information about the data transaction in the channel. Perhaps its a read completion, or a write status word.
Let’s assume our example should copy the data. So, what then is deep copy ? A deep copy is a recursive replication of the members in the class/struct. For example, if our data between the generator and driver/checker was a list of blocks of lower level random data to be sent, both the list and the blocks would be copied.
A shallow copy, by contrast, would only copy the list. A shallow copy does not recurse beyond the “top level” object (the one being copied). In our example, there would only be one instance of the blocks of lower level data.
If your data only consists of integral types, there is no difference between deep and shallow copy. If there are pointers in your class/struct then you need to think about what you want to happen.
Now, if you data has ANY virtual functions (i.e. not just a clump of data), then you really need to think. My general rule is that you are probably doing something wrong. Go back and rethink why your design needs both virtual data members and needs to copy.
If you really do need to copy a class/struct with virtual methods, you generally end up with a two method scheme. One method “makes/news” the right type of object (because this is a virtual method) and the second method copies the data. Pretty darn horrible.
My general advice is to use pointers for most things in a channel. Then you do not have to worry about copying. But if you do have to copy, make sure you think about all the members, data and methods.
HI,
I’m currently using Cadence Incisive (ncsim) to run the example block_uart in the “truss systemverilog version 1.62 ” ,which gets some compile errors. It seems the script truss about ncsim in the directory of bin has some erros.
the part of the script:
elsif (uc $ENV{SIM} eq “NCSIM”){
#
# NCSIM
#
………
$compile_hdl = (”cd $RESULT_DIR; mkdir ncvlog_lib; ” .
“echo DEFINE ncvlog_lib ./ncvlog_lib > cds.lib; ” .
“echo DEFINE WORK ncvlog_lib > hdl.var; ” .
“ncvlog $ENV{\”PROJECT_HOME\”}/verification/testbench/$config/testbench.v -WORK ncvlog_lib ” .
“-f $ENV{\”PROJECT_HOME\”}/verification/testbench/$config/hdl_paths.ncsim ;” .
“ncelab -REDUCE_MESSAGES -NOCOPYRIGHT -ARR_ACCESS -ACCWARN -LIBNAME ncvlog_lib -LOGFILE ncelab.log -access +RWC ncvlog_lib.top -SNAPSHOT ncvlog_lib.ncvlog_lib:ncvlog_lib”);
truss_system ($compile_hdl);
}
I had changed it by add some args ,eg: -sv, but many errors again. Do you guys has a better success script
to support ncsim in systemverilog?
Thanks,
wheater
Hi,
Can any one tell me which version of modelsim supports codecoverage option.
Actually i am using modelsim 6.3f[Special Edition] version. I face problems when trying do a codecoverage.
I would like to know the version number and edition number for both verilog and System verilog.
Regards,
Aathi
I wasn’t quite sure where to post this in the forum so here it goes.
My question has to do with interfacing a Verilog testbench to a VHDL DUT. This is easy to do when the VHDL entity has normal port signals such as bit_vector, std_logic_vector, and std_logic. However to keep my design clean I make extensive use of records in VHDL. This has caused considerable headache when I try to instantiate the VHDL entity in the verilog testbench, which I still haven’t figured out how to do. I’m by no means a verilog expert but I did find out that verilog does not have an equivalent to records, just a way of faking them. I was wondering if the designers of Teal had run into the same problem and what solutions they ended up using?
Thanks,
Brian
What about the Truss/Teal donation to the committee ?
May 26
I’m not quite sure if this question has been asked before but I’d like to hear what the opinion of the user group is. For verification of a SoC design, what are the pros and cons of using a C++/SystemC based method as opposed to SystemVerilog? I have about equal experience in C programming and VHDL so it’s going to require a certain amount of learning to get either approach up and running. But what I’m looking for is some opinions as to what people have found to work for them, what industry seems to be gravitating to, and perhaps additional resources that would give me a better defined reasons to pick one over the other.
Thanks,
Brian
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